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19-3535; Rev 0; 1/05
MAX19542 Evaluation Kit
General Description
The MAX19542 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX19541 (125Msps) and MAX19542 (170Msps) 12-bit analog-to-digital converters (ADCs). The MAX19542 accepts differential analog inputs; however, the EV kit generates this signal from a user-provided single-ended signal source. The digital outputs produced by the ADC are CMOS compatible and can be easily captured with a user-provided, high-speed logic analyzer or dataacquisition system. The EV kit operates from 1.8V and 3.3V power supplies and includes circuitry that generates a clock signal from a user-provided AC signal.
Features
o Up to 170Msps Sampling Rate Using the MAX19542 o Up to 125Msps Sampling Rate Using the MAX19541 o Low-Voltage and Low-Power Operation o Fully Differential Input Signal Configuration o On-Board Output Buffers o Fully Assembled and Tested
Evaluates: MAX19541/MAX19542
Ordering Information
PART MAX19542EVKIT TEMP RANGE 0C to +70C IC PACKAGE 68 QFN-EP*
Note: To evaluate the MAX19541, request a free sample with the MAX19542 EV kit. *EP = Exposed paddle.
Component List
DESIGNATION C1, C2, C3, C5-C27 C4 QTY 26 DESCRIPTION 0.1F 10%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104K Not installed, ceramic capacitor (0402) 0.22F 10%, 6.3V X5R ceramic capacitors (0402) TDK C1005X5R0J224K 47F 10%, 10V tantalum capacitors (C case) AVX TAJC476K010 10F 20%, 6.3V X5R ceramic capacitors (0805) TDK C2012X5R0J106M 1.0F 10%, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A105K 0.01F 20%, 25V X7R ceramic capacitor (0402) TDK C1005X7R1E103M Not installed, shorted by PC trace (0603) Not installed, ceramic capacitors (0603) DESIGNATION INP, CLK, RESET INN J1, J2 JU1-JU6, JU8 JU7 R1, R2, R11, R12, R14, R15, R22 R3-R7 R8, R9 R10, R13 R16, R17 C39-C42 4 R18, R19 R20 C43 1 R21 R23-R26 RA1-RA4 QTY 3 0 2 7 1 0 5 2 2 2 2 1 1 0 4 DESCRIPTION SMA PC board vertical-mount connectors Not installed, vertical-mount SMA connector Dual-row 40-pin headers 3-pin headers Dual-row 8-pin header Not installed, resistors (0603) 49.9 1% resistors (0603) 510 5% resistors (0603) 0 resistors (0603) 24.9 0.1% resistors (0603) IRC PFC-W0603R-02-24R9-B 24.9 1% resistors (0603) 100k, 12-turn, 1/4in potentiometer 13k 1% resistor (0603) Not installed, shorted by PC trace (0603) 100 5% resistor arrays (1206) Panasonic EXB-2HV-101J
0
C28, C29, C30
3
C31-C34
4
C35-C38
4
C44, C45 C46, C47
0 0
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Component List (continued)
DESIGNATION RA5-RA8 T1, T2 TP1, TP2, TP3 U1 QTY 4 2 3 1 DESCRIPTION 22 5% resistor arrays (1206) Panasonic EXB-2HV-220J 1:1 800MHz RF transformers Mini-Circuits ADT1-1WT Test points (black) MAX19542EGK (68-pin QFN, 10mm x 10mm) 3.3V ECL differential receiver (8-pin SO) ON Semiconductor MC100LVEL16D U5 None 1 1 DESIGNATION QTY DESCRIPTION Low-voltage, 16-bit flip-flops (48-pin TSSOP) Pericom PI74ALVTC16374A48 Digi-Key PI74ALVTC16374A-ND Dual two-input exclusive-OR gate (8-pin VSSOP) TI SN74AUC2G86DCUR MAX19542 PC board
U3, U4
2
U2
1
Component Suppliers
SUPPLIER AVX IRC Panasonic TDK PHONE 843-946-0238 361-992-7900 714-373-7183 847-803-6100 FAX 843-626-3123 361-992-3377 714-373-7939 847-390-4405 WEBSITE www.avxcorp.com www.irctt.com www.panasonic.com www.component.tdk.com
Note: Indicate that you are using the MAX19541/MAX19542 when contacting these component suppliers.
Quick Start
Recommended Equipment
* DC power supplies: Analog (AVCC) 1.8V, 1A
1)
Verify that shunts are installed in the following locations: a) JU1 (1-2)--Divide-by-two disabled b) JU2 (2-3)--Parallel mode selected c) JU3 (2-3)--Demux parallel mode selected if JU2 is pulled high d) JU4 (2-3)--Two's-complement output selected e) JU5 (1-2)--Noninverted DCLKP selected f) JU6 (2-3)--Noninverted DCLKN selected g) JU7 (3-4)--Internal reference enabled
Clock (CVCC) 3.3V, 500mA Buffers (BVCC) 1.8V, 500mA Digital (OVCC) 1.8V, 1A * Signal generator with low phase noise for clock input signal (e.g., HP 8662A, HP 8644B) * Signal generator for analog input signal (e.g., HP 8662A, HP 8644B) * Logic analyzer or data-acquisition system (e.g., HP 16500C with high-speed state card (e.g., HP 16517A) * Digital voltmeter 2) 3) 4)
Connect the clock signal generator to the SMA connector labeled CLK. Connect the analog input signal generator to the SMA connector labeled INP. Connect the logic analyzer's high-speed state card probe connectors to header J1 (CMOS-compatible signals); see Table 5 for header connections. Connect a 1.8V, 1A power supply to AVCC. Connect the ground terminal of this supply to the GND pad closest to the AVCC pad.
Procedure
The MAX19542 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable signal generators until all connections are completed: 5)
2
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MAX19542 Evaluation Kit
Connect a 3.3V, 500mA power supply to CVCC. Connect the ground terminal of this supply to the GND pad closest to the CVCC pad. 7) Connect a 1.8V, 500mA power supply to BVCC. Connect the ground terminal of this supply to the GND pad closest to the BVCC pad. 8) Connect a 1.8V, 1A power supply to OVCC. Connect the ground terminal of this supply to the GND pad closest to the OVCC pad. 9) Turn on all the power supplies. 10) Enable the signal generators. Set the clock signal generator to output a 170MHz signal, with a 2.4VP-P amplitude. Set the analog input signal generator to output the desired frequency with an amplitude 2V P-P . The signal generators should be synchronized. 11) Enable the logic analyzer. 12) Collect data using the logic analyzer. 6)
Power Supplies
The MAX19542 EV kit requires separate analog, digital, clock, and buffer power supplies for best performance. Two separated 1.8V power supplies are used to power the analog and digital portions of the MAX19541/ MAX19542. The on-board clock circuitry is powered by another 3.3V power supply, and a 1.8V power supply is used to power the output buffers (U3 and U4) on the EV kit.
Evaluates: MAX19541/MAX19542
Clock
The MAX19541/MAX19542 require a differential clock signal. However, if only a single-ended clock signal source is available, the EV kit's on-board level translator helps to convert a single-ended clock to the required differential signal. An on-board clock-shaping circuit generates a differential clock signal from an AC-coupled sinewave signal applied to the clock input SMA connector CLK. The input signal amplitude should not exceed 2.6VP-P. The frequency of the clock signal should not exceed 170MHz. The frequency of the sinusoidal input clock signal determines the sampling frequency (fCLK) of the ADC. A differential line receiver (U2) processes the input signal to generate the required clock signal. Clock Divider The MAX19541/MAX19542 feature an internal divideby-two clock divider. Use jumper JU1 to enable/disable this feature. See Table 1 for shunt positions.
Detailed Description
The MAX19542 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX19542. The MAX19542 can be evaluated with a maximum clock frequency (fCLK) of 170MHz. The MAX19542 accepts differential inputs. Applications that only have a single-ended signal source available can use the on-board transformer (T2) to convert a singleended signal to a differential signal. Output buffers (U3 and U4) buffer the digital output signals of the MAX19542 to higher capacitive load signals that can be captured by a wide variety of logic analyzers. The buffered CMOS outputs can be accessed at headers J1 and J2. The EV kit is designed as a four-layer PC board to optimize the performance of the MAX19542. Separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals; 50 coplanar transmission lines are used for analog and clock inputs. The trace lengths of the 50 CMOS lines are matched to within a few thousandths of an inch to minimize layout-dependent delays.
Table 1. Clock-Divider Shunt Settings (JU1)
SHUNT POSITION 1-2 (default) 2-3 MAX19542 CLKDIV PIN Connected to AVCC Connected to GND DESCRIPTION Clock signal divided by 1 Clock signal divided by 2
Input Signal
The MAX19541/MAX19542 accept differential analog input signals. However, the EV kit only requires a single-ended analog input signal with an amplitude of less than 2VP-P provided by the user. An on-board transformer then takes the single-ended analog input and generates a differential analog signal, which is applied to the ADC's differential input pins.
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3
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Optional Input Transformer The MAX19452 EV kit uses a second transformer to enhance THD and SFDR performance at high input frequencies (>100MHz). This transformer helps to reduce the increase of even-order harmonics at high frequencies. To use only the primary transformer, follow the directions below: 1) 2) 3) 4) 5) Remove R10 and R13. Install a 0.1F capacitor on C4. Install a 0 resistor at R22. Install an SMA connector on INN. Connect the analog signal source to INN instead of INP.
Reference Voltage
There are two methods to set the full-scale range of the MAX19541/MAX19542. The MAX19542 EV kit can be configured to use the MAX19542's internal reference, or a stable, low-noise, external reference can be applied to the REFIO pad. Jumper JU7 controls which reference source is used. See Table 2 for shunt settings.
Output Mode
The MAX19541/MAX19542 feature three modes of operation: parallel mode, demux parallel mode, and demux interleaved mode. In each mode of operation, the digital data is output in a different format and is controlled by the ADC's DEMUX and ITL pins. The EV kit incorporates jumpers JU2 and JU3 to control the DEMUX and ITL pins, respectively. See Table 3 for shunt settings. Output Format The digital output coding can be chosen to be either in two's complement or straight offset-binary format by configuring jumper JU4. See Table 4 for shunt settings.
Table 2. Reference Shunt Settings (JU7)
SHUNT POSITION 1-2 3-4 (default) 5-6 7-8 DESCRIPTION Internal Reference Disabled. Apply an external reference voltage to the REFIO pad. Internal Reference Enabled. REFIO is the output of the internal reference. Increases FSR through trim potentiometer R20. Decreases FSR through trim potentiometer R20.
Table 3. Output-Mode Shunt Settings (JU2 and JU3)
JU2 SHUNT POSITION 2-3 1-2 1-2 DEMUX PIN Connected to GND Connected to AVCC Connected to AVCC JU3 SHUNT POSITION -- 2-3 1-2 -- Connected to GND Connected to AVCC ITL PIN OUTPUT MODE Parallel mode Demux parallel mode Demux interleaved mode OUTPUT PORT Port A Ports A and B Ports A and B
Table 4. Output-Format Shunt Settings (JU4)
SHUNT POSITION 1-2 2-3 (default) T/B Pin Connected to AVCC Connected to GND DESCRIPTION Digital data appears in straight offset-binary code. Digital data appears in two's-complement code.
4
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MAX19542 Evaluation Kit
Output Bit Locations The buffered digital outputs of the ADC are connected to two 40-pin headers (J1 and J2). PC board trace lengths are matched to minimize output skew and improve performance of the device. The buffers are able to drive large capacitive loads, which may be present at the logic analyzer connection. See Table 5 for headers J1 and J2 bit locations.
Evaluates: MAX19541/MAX19542
Table 5. Output Bit Locations
PORT A BIT ORA DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DCLKP BUFFERED OUTPUT J1-35 J1-31 J1-29 J1-27 J1-25 J1-23 J1-21 J1-19 J1-17 J1-15 J1-13 J1-11 J1-9 J1-3 LABEL NAME BORA BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 CLKA PORT B BIT ORB DB11 DB10 DB9 DB9 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DCLKN BUFFERED OUTPUT J2-35 J2-31 J2-29 J2-27 J2-25 J2-23 J2-21 J2-19 J2-17 J2-15 J2-13 J2-11 J2-9 J2-3 LABEL NAME BORB BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 CLKB Bit 0 (LSB) Clock output signal Bits 10-1 DESCRIPTION Overrange bit Bit 11 (MSB)
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5
Evaluates: MAX19541/MAX19542
AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC
R25 SHORT 7 CLKA INP 1 1 TP1 5 R12 OPEN 9 INN C47 OPEN C2 0.1F 3 R19 24.9 1% 4 C3 0.1F R17 24.9 0.1% 2 6 5 R1 OPEN 3 4 2 1 T1 6 2 R11 OPEN T2 R16 24.9 0.1% C46 OPEN 8 INP ORA DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 C6 0.1F DA3 DA2 DA1 22 CLKN 7 R4 49.9 1% C7 R6 49.9 0.1F 1% U1 R5 49.9 Q6 1% VBB R8 510 C43 0.01F VEE C8 0.1F RESET 1 2 AVCC JU7 C22 0.1F C23 0.1F REFADJ JU7-3 JU7-4 JU7-6 JU7-8 3 R20 100k 1 C26 0.1F C27 0.1F 2 JU7-5 JU7-7 JU7-1 JU7-2 REFADJ AVCC 15 RESET DA0 ORB DB11 DB10 DB9 1A 1Y U5 SN74AUCG286DCUR 2A 2Y CLKB 3 C1 0.1F
R18 24.9 1% OVCC OVCC OVCC OVCC OVCC 59 58 57 56 55 54 53 52 51 50 49 48 47 46 40 39 38
MAX19542 Evaluation Kit
Figure 1. MAX19542 EV Kit Schematic (Sheet 1 of 2)
1.8V 1.8V AVCC C35 10F C39 1.0F GND GND C36 10F C40 1.0F GND C42 1.0F C38 10F C41 1.0F C37 10F OVCC CVCC 3.3V BVCC BVCC AVCC 1.8V CVCC OVCC GND C31 47F 10V C32 47F 10V C34 47F 10V C33 47F 10V AVCC INN 1 R23 SHORT TP2 R10 0 R14 OPEN C44 SHORT 1 6 11 12 13 14 20 25 63 65 62 27 28 41 44 60 R2 OPEN BVCC 2 1B C10 0.1F VCC 8 C4 OPEN OVCC ORA DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 ORB DB11 DB10 DB9 2B GND R13 0 R22 OPEN CVCC R15 OPEN C45 SHORT 4 C28 0.22F C29 0.22F 2D Q C13 0.1F C16 0.1F C14 0.1F C15 0.1F R9 510 1 N.C. 8 VCC CLK 1 3D R3 49.9 1% 2 C18 0.1F C19 0.1F C5 0.1F U2 MC100LVEL16
AGND AGND AGND AGND AGND AGND AGND AGND AGND
2 5 7 10 18 19 21 64 24
OGND OGND OGND
26 45 61
66 R24 SHORT
AGND
6
MAX19542
23 CLKP DB8 DB7 DB6 DB5 DB4 DB3 R7 49.9 1% 1 2 3 JU1 17 CLKDIV DB2 DB1 DB0 DCLKP REFIO 3 C9 0.1F 4 REFADJ DCLKN REFIO DEMUX 37 36 35 34 33 32 31 30 29 43 42 16 AVCC 67 ITL R21 13k 1% REFADJ TP3 T/B 68 JU4 AVCC 1 2 3 JU3 1 2 3 TVB DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DCLKP DCLKN JU2 1 2 3 ITL AVCC
BVCC
1 2 3
JU5
2
DCLKP
1
R26 SHORT
DCLKN
5
BVCC
1 2 3
JU6
6
AVCC
C11 0.1F
C12 0.1F
PLACE CAPACITORS NEXT TO PINS 1, 6, 11/12, 13/14, 20, 25, 63, 65 OF U1.
OVCC
C30 0.22F
C17 0.1F
PLACE CAPACITORS NEXT TO PINS 26/27, 41, 44, 60 OF U2.
BVCC
C20 0.1F
C21 0.1F
PLACE CAPACITORS NEXT TO PINS 7, 18, 31, 42 OF U3.
BVCC
_______________________________________________________________________________________
C24 0.1F
C25 0.1F
PLACE CAPACITORS NEXT TO PINS 7, 18, 31, 42 OF U4.
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
BVCC CLKA CLKA
48 1CLK RA1 100 1 2 3 ORA DA11 DA10 DA9 DA8 4 5 6 7 8 RA2 100 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 37 38 40 41 43 44 46 47 1 24 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1OE 2OE GND 16 15 14 13 12 11 10 9 26 27 29 30 32 33 35 36 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1
7 VCC
18 VCC
31 VCC
42 VCC
48 2CLK RA5 22 23 22 20 19 17 16 14 13 1 2 3 4 5 6 7 8 RA6 22 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 12 11 9 8 6 5 3 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 J1-23 J1-21 J1-19 J1-17 J1-15 J1-13 J1-11 J1-9 J1-7 J1-5 J1-24 J1-22 J1-20 J1-18 J1-16 J1-14 J1-12 J1-10 J1-8 J1-6 J1-4 J1-2 16 15 14 13 12 11 10 9 J1-39 J1-37 J1-35 J1-31 J1-29 J1-27 J1-25 J1-33 J1 J1-40 J1-38 J1-36 J1-32 J1-30 J1-28 J1-26 J1-34
2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 U3 PI74ALVC16374 2Q1
GND
GND
GND
GND
GND
GND
GND
CLKA
J1-3 J1-1
4 10 15 21 28 34 45 39
BVCC CLKB CLKB
48 1CLK RA3 100 1 2 3 ORB DB11 DB10 DB9 DB8 4 5 6 7 8 RA4 100 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BVCC 1 1 JU8 2 3 24 1OE GND 37 38 40 41 43 44 46 47 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 16 15 14 13 12 11 10 9 26 27 29 30 32 33 35 36 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1
7 VCC
18 VCC
31 VCC
42 VCC
48 2CLK RA7 22 23 22 20 19 17 16 14 13 1 2 3 4 5 6 7 8 RA8 22 1Q8 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q1 12 11 9 8 6 5 3 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 J2-23 J2-21 J2-19 J2-17 J2-15 J2-13 J2-11 J2-9 J2-7 J2-5 CLKB J2-3 J2-1 J2-24 J2-22 J2-20 J2-18 J2-16 J2-14 J2-12 J2-10 J2-8 J2-6 J2-4 J2-2 16 15 14 13 12 11 10 9 J2-39 J2-37 J2-35 J2-31 J2-29 J2-27 J2-25 J2-33 J2 J2-40 J2-38 J2-36 J2-32 J2-30 J2-28 J2-26 J2-34
2Q8 2Q7 2Q6 2Q5 2Q4 2Q3 2Q2 U4 PI74ALVC16374 2Q1
GND
GND
GND
GND
GND
GND
4 10 15 21 28 34 45 39
Figure 1. MAX19542 EV Kit Schematic (Sheet 2 of 2) _______________________________________________________________________________________ 7
GND
2OE
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 2. MAX19542 EV Kit Component Placement Guide--Component Side 8 _______________________________________________________________________________________
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 3. MAX19542 EV Kit PC Board Layout--Component Side
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9
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 4. MAX19542 EV Kit PC Board Layout--Ground Plane (Inner Layer 2) 10 ______________________________________________________________________________________
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 5. MAX19542 EV Kit PC Board Layout--Power Planes (Inner Layer 3)
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11
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 6. MAX19542 EV Kit PC Board Layout--Solder Side 12 ______________________________________________________________________________________
MAX19542 Evaluation Kit Evaluates: MAX19541/MAX19542
Figure 7. MAX19542 EV Component Placement Guide--Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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